1. Technical Field
This disclosure relates to a constant voltage circuit, and more particularly to a constant voltage circuit capable of making a quick response to a wide range of output currents such as a minute current and a large current, and capable of stable operation with high efficiency.
2. Description of the Related Art
In electronic devices such as portable phones, mobile PCs, and car navigation systems, a constant voltage power source having a constant voltage circuit and capable of supplying a stable voltage is used as a power source. When using such a constant voltage power source in a device with a large output current, the constant voltage power source is required to have a circuit configured to realize a high speed response by improving a ripple removing ratio and a load transient response. For example, when the constant voltage power source is used in a device with a wide range of output current, such as a portable phone having an operation mode and a standby mode, a circuit configuration capable of receiving a maximum output current is required. As a result, a current consumption is increased as a whole. In the standby mode of the portable phone, in which a high ripple removing ratio and a high load transient response are not required, an unnecessary current is consumed, which results in increasing the wasted current. In view of this, a constant voltage circuit for suppressing this wasted power consumption has been suggested.
Each of Patent Documents 1 and 2 discloses a constant voltage circuit configured to increase or decrease a bias current supplied to a differential amplifier in the constant voltage circuit depending on the amount of output current.
FIG. 8 shows the constant voltage circuit disclosed in Patent Document 1. In FIG. 8, a constant voltage circuit 101 includes a reference voltage circuit Vref, a differential amplifier circuit 102, a bias current generating circuit 103, and an output circuit 104.
In this circuit, a PMOS transistor M7 and an output transistor M1 form a current mirror circuit. Therefore, a drain current in proportion to a drain current (output current) of the output transistor M1 is generated in the PMOS transistor M7. This current is supplied as a drain current of an NMOS transistor M8. Since the NMOS transistor M8 and an NMOS transistor M9 form a current mirror circuit, a drain current of the NMOS transistor M9 is in proportion to the drain current of the output transistor M1. The drain current of the NMOS transistor M9 is a part of a bias current of the differential amplifier circuit 102, therefore, the bias current of the differential amplifier circuit 102 increases and decreases in accordance with an increase and a decrease of the output current.
In this manner, the bias current of the differential amplifier circuit 102 is increased and decreased in accordance with the increase and decrease of the output current. Therefore, a response speed is increased when the output current is increased. In this manner, the current consumption and the response speed are set appropriately.
[Patent Document 1] Japanese Patent Application Publication No. 3-158912
[Patent Document 2] Japanese Patent Application Publication No. 2006-99526
In the constant voltage circuits configured to change the bias current of the differential amplifier circuit in accordance with the output current as disclosed in Patent Documents 1 and 2, an operation of the constant voltage circuit becomes unstable when the output current is small. That is, for example, a constant voltage power source having a large output transistor a capable of outputting an output current of 1 A or more can be stably operated when the output current is large. However, this constant voltage power source cannot be stably operated when the output current is small since a bias current of a differential amplifier circuit becomes small and a phase margin is decreased. Moreover, there is a problem in that a response speed is extremely low when the bias current is small. This is because a transistor having a large ratio of gate width to gate length and thus having large gate capacitance is used as an output transistor to realize an operation with a large current. When a bias current is small, it takes time to charge and discharge the gate capacitance. Therefore, the response speed is drastically decreased when the output current is small.